DIY Night Clock Projector

A Clock Projector can project the time to a ceiling in the night.

DSC00244

There are lots of commercial alarm clocks with integrated clock projector on the market but I thought, it would be fun to build one myself.

Moreover it was a good project for becoming accustomed to the process of 3d-designing cases which can be 3d printed and to learn about designing tolerances.

The principle is easy – basically it works like a video beamer (or any other projecting clock^^).

principle

LCD and Calculations

I choosed a small negative (background black) 64×32 LCD which has the dimensions of just 15mm x 12mm (active area 11.18mm x 5.58mm).

lcd

The goal was to build a complete projector with not more than 50mm x 50mm x 50mm (which I didn’t managed … But close to^^).

A small LCD has the advantage that everything becomes smaller and cheaper – this influences heavily costs for optics because a smaller LCD needs smaller optics to project an low distorted image.

Moreover a smaller LCD needs smaller focal length for a decent sized imaged on the ceiling. A good distance would be 2m from LCD to ceiling.

The formula for image width depending from the focal length is defined as:

Lens3.svg

\frac{1}{f}=\frac{1}{S_1}+\frac{1}{S_2}\hspace{20mm}\frac{W_1}{W_2}=\frac{S_1}{S_2}

with:
– S2 distance from lens to LCD and
– S1 distance from lens to ceiling
– W2 is the width of the LCD
– W1 is the width of the projected image

The formulas show that the smaller the focal length the larger the projected image will be.

I decided to go for 25mm because there are cheap lenses which can be obtained for about $12 in china.

For our values that would magnify the image by about x80 – 11.1mm LCD width would become 88.1cm image width on the ceiling in a distance of 2m.

Light and Condensor Lens

It was not really clear how strong a LED has to be in order to get a reasonable well readable picture in the night on the ceiling.

To be sure – actually I wasn’t really – I decided to use a high power LED with 1W and use a cheap chinese condensor lense to parallelize the light before it passes the LCD (this has do be done anyway but a condensor lens makes it possible to use more light because condensors are shaped in a way that allowes to get the lens as near to the LED as possible – so catching more light).

The two pictures show the condensor-lense which is directly mounted to the PCB the resulting light spot on the ceiling. It is a really gread lens which is made for my LED – so it fits perfectly and parallelizes the light nicely.

Electronics Construction

Two PCBs were designed – one holding the LCD and the actual projecting board.

The latter is equipped with 1W LED driver, STM32F103 Cortex ARM, a rotary encoder (for changing settings like brightness, standby-timer, time, …), USB, IR (both not used yet).

Mechanics Construction

Originally, I aimed for 50mm x 50mm x 50mm but I only managed to get to 60mm x 60mm x 60mm 😥 😉

Here an overview about all I designed:

Spectacle.J23956

From left to right: Case with DIY projection lens (I skip this part – it worked but not really well), Sony E-Mount, C-Mount. In the middle the rest.

LCD-Holder

A custom LCD-holder was designed to perfectly mount the LCD on the right place on the PCB.

Case – C-Mount Variant

There are incredibly cheap chinase C-Mount lenses with a focal length of 25mm. They are sooo cheap that image quality is really really bad when using for fotography.

23380257_1223416981124165_4793755427854490814_n

But surprisingly it works (almost) perfect for the Mini DIY Projector 😀

23559568_1223771867755343_5931761190105667111_n

The pillow-effect (optical distortion where the edges are not straight but bent outwards) is almost neglectable – resulting a much better image than I expected (after reading reviews to this lense)

23559460_1223772024421994_2585757183464992038_n

Case – Sony E-Mount Variant

Just for fun – and because I have a 3d printer which works reliably without much attention – I did a variant for Sony E-Mount.

Spectacle.Tw9321

Here the projector with Walimex Pro 10mm 2.8 lens.

23380218_1219804668152063_8622113328646516671_n

I have to admit – it isn’t that bright in reality but it’s still very readable although it is so large.

DSC00244

The image has more than 2m in width! And distortions almost non-existent 🙂

Downloads

Followig GitHub-Repository contains:
Schematic
Layout
Bill of material
STM32 Cortex ARM Source
3D-STL-Files
Images

Link to GitHub Repository

STL-Files on Thingiverse

Support

If you like my work and want to support me please consider to donate some (M)IOTAs to following IOTA address:

LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY

With your donation you help me to cover my costs and enable me to further develop interesting projects which mostly need much time and financial resources 🙂

 

IOTA PoW Hardware Accelerator FPGA for Raspberry Pi (und USB)

DSC08600_DSC08601_DSC08602__enfuseUpdates:

2018-07-12: Demonstration Video online. Also, there is now a CCurl-compatible shared library for the USBDiver (e.g. for Light Wallet or NodeJS)
2018-07-01: Additional to the „Raspberry-Pi-Mode“ the PiDiver can now be used with USB – no Pi needed.  (video)
2018-06-25: Roman Semko’s Hercules got FPGA support (First confirmed Transaction , Roman’s Tweet)
2018-06-19: Core extended with CRC32 to recognize SPI transfer errors of Trytes for Mid-State calculation.
2018-06-06: Next prototypes will be assembled machinally. ESD-protection & EMI-filtering added. It should be compliant to CE when tested.
2018-06-04: Current measurement revealed, the PiDiver needs less than 2W power and can be powered by standard USB.
2018-06-01: Migrated Altera DE1 Proof-Of-Concept in another article in order to clean up obsolete informations. (You can find it here)
2018-05-31: Changed License to MIT and added board, schematic, gerber, BOM (with order-numbers), … files to Repository.
2018-05-27: Curl-P81 mid-state now calculated on FPGA; Mid-State takes about 7ms, PoW reaches about 15.8MH/s @ 188MHz. FPGA resource utilization ist about 98% …^^
2018-05-17: It’s alive *muahaha* It’s working fine and reaching about 14.6MH/s
2018-05-07: Some optimisations … Reaching 12.9MH/s on Altera DE1
2018-05-04: Installation instructions for Raspberry Pi added
2018-05-03: Major core optimizations – reaching now about 12MH/s.

Introduction

IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. One of the main reasons is that the innerst loop of Curl-P81 can’t be computed very efficient on general purpose CPUs. Even modern CPUs with SIMD extension (like SSE or AVX) are heavily restricted when it comes to true parallel calculations.

This is a port of IOTA IRI’s Pearl-Diver for PoW-computation for FPGAs which speeds up the process of doing Proof-Of-Work significantly by a factor of more than 140 compared to e.g. a Raspberry Pi.

The core concept is that FPGAs are  able to calculate one round of Curl-P81 in a single clock cycle and one complete Hash in about 85 (including test for valid nonce). The core works 7-fold which means, in every 85 clock cycles 7 Hashes are calculated in parallel – this gives about 15.8MHash/s at a clock frequency of 188MHz. Moreover, the parallel computation can be adjusted easily to be even faster on larger FPGAs.

For instance, finding the nonce of a single transaction takes about 90s on a Raspi. Finding the nonce hardware accelerated by this core reduces the time to ~300ms.

This core can be also used by IRI when using a modified version which allows to use dcurl as external hashing libary.

So it is possible to build a full-node on raspberry pi with a decent hashing power for doing PoW calculations.

The project aims to be completly open source including all source codes, schematic, layouts.

VHDL-Core

The IOTA PoW Pearl-Diver core was implemented in VHDL.

Except an Altera PLL, no additional core or unusual VHDL library is used which makes it very simple to implement for other FPGA platform targets.

Moreover the core is customizable so the 7-fold parallelization can be increased or reduced (above 8, more cores should be instanciated because routing could fail or lead to very slow clock frequencies) depending on the resources of a FPGA target.

There is an additional (slower) 1-fold Curl which is used to calculate the mid-state.

The core implements a high-speed SPI interface which directly can be used by the hardware SPI of a Raspberry Pi.

Here the synthesis report for the Cyclone 10LP (10CL025):

Spectacle.J24487

Pearl-Diver Core Repository

The repository contains everything which is needed for rebuilding the PiDiver:

  • KiCad Board & Schematic Files
  • Gerber Files
  • Schematic as PDF
  • Component Placement as PDF with some notes
  • BOM with distributors and order numbers
  • VHDL code and project for (free) Quartus 17.x

Link to Github Repository

Hashing-Library dcurl with FPGA support

dcurl is a very fast Curl-Hashing-Library which not only supports graphics cards (OpenCL) but also provides highly optimized variants for SSE and AVX capable CPUs.

I did a fork of the library and added code for support of the VHDL Pearl-Diver.

The advantage is that every software working together with dcurl library can make use of the FPGA version of Curl (on Raspberry Pi – for different targets the low level control of SPI has to be replaced).

Link to Github Repository

Compiling and Testing with dcurl

1. Download and install BCM2835 library

# download the latest version of the library, say bcm2835-1.xx.tar.gz, then:
tar zxvf bcm2835-1.xx.tar.gz
cd bcm2835-1.xx
./configure
make
sudo make check
sudo make install

2. Enable „SPI“ under „Interfacing Options“.

sudo raspi-config

3. Load kernel module with modprobe

sudo modprobe spi_bcm2835

4. Check Permissions

pi@raspi:~ $ ls /dev/spidev0.0 -al
crw-rw---- 1 root spi 153, 0 May 3 15:17 /dev/spidev0.0

pi@raspi:~ $ groups
pi adm dialout cdrom sudo audio video plugdev games users input netdev gpio i2c spi

5. Clone and Compile dcurl library

git clone https://github.com/shufps/dcurl
cd dcurl
make BUILD_FPGA=1

6. Test library (for a reason I still don’t know SPI access only with „sudo“ possible).

cd build
sudo ./test-pow_fpga

Found nonce: 0004f6ee (mask: 00000008) 
Mid-State Time:   11ms 
PoW Time:        144ms  -  MH/s: 15.816

7. If there is no error then everything worked 🙂

Performance

Finding a valid nonce is completly random, so it can happen that finding needs up to multiple of seconds – but it also can happen that it takes almost no time at all.

Following a histogram for the PoW-time of 10,000 transactions.

In the x-Axis there is the time of PoW and in the y-axis the number of transactions which needed this time.

histogram

25% of all nonces are found within 87ms
50% of all nonces are found within 200ms
75% of all nonces are found within 433ms

It’s quite surprising that the PoW-time is not normally distributed (what I actually expected).

The PiDiver needed 50 minutes for 10,000 transactions – making about 3,33 PoW per second and giving an average of 300ms.

Support

If you like my work please consider to donate some MIOTAs to:

LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY

Discord: pmaxuw#8292

Licence

This project is licensed under the MIT-License

[OLD] IOTA PoW Hardware Accelerator FPGA for Altera DE1

poc

This is the site for the obsolete Altera DE1 proof-of-concept. Please look here for the PiDiver

Introduction

IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. One of the main reasons is that the innerst loop of Curl-P81 can’t be computed very efficient on general purpose CPUs. Even modern CPUs with SIMD extension (like SSE or AVX) are heavily restricted when it comes to true parallel calculations.

This is a port of IOTA IRI’s Pearl-Diver for PoW-computation for FPGAs which speeds up the process of doing Proof-Of-Work significantly by a factor of more than 140 compared to e.g. a Raspberry Pi.

The core concept is that FPGAs are  able to calculate one round of Curl-P81 in a single clock cycle and one complete Hash in about 85 (including test for valid nonce). The core works 5-fold which means, in every 85 clock cycles 5 Hashes are calculated in parallel – this gives about 12.87MHash/s at a clock frequency of 220MHz. Moreover, the parallel computation can be adjusted easily to be even faster on larger FPGAs.

For instance, finding the nonce of a single transaction takes about 90s on a Raspi. Finding the nonce hardware accelerated by this core reduces the time to ~350ms.

This core can be also used by IRI when using a modified version which allows to use dcurl as external hashing libary.

So it is possible to build a full-node on raspberry pi with a decent hashing power for doing PoW calculations.

The project aims to be completly open source including all source codes, schematic, layouts.

VHDL-Core

The IOTA PoW Pearl-Diver core was implemented in VHDL.

 

Except an Altera PLL, no additional core or unusual VHDL library is used which makes it very simple to implement for other FPGA platform targets.

Moreover the core is customizable so the 5-fold parallelization can be increased or reduced (currently up to 8 but that could be changed with little work) depending on the resources of a FPGA target.

The core implements a high-speed SPI interface which directly can be used by the hardware SPI of a Raspberry Pi.

Following the electrical connections between Altera DE1 and Raspberry Pi.

Spectacle.J20765

Here the synthesis report for the EP2C20:

Spectacle.J21867

Maximum clock frequency:

Spectacle.J21835

First clock is I/O like SPI and commando decoder (running @ 110MHz in the design). Second clock is the actual Pearl-Diver PoW State-Machine reaching 220MHz.

Design is still functional although all of the optimizations 🙂

Pearl-Diver Core Repository

Following repository not only contains VHDL source for Altera DE1 and „Pi-Diver“ proto-type but also project-files for Quartus (Prime).

Altera DE1 Cyclone 2 is supported by Quartus 13.0.1 and Cyclone 10 is supported by Quartus 17.x. In the first case, you can directly synthesize the project and upload it to the Altera DE1.

Link to Github Repository

Hashing-Library dcurl with FPGA support

dcurl is a very fast Curl-Hashing-Library which not only supports graphics cards (OpenCL) but also provides highly optimized variants for SSE and AVX capable CPUs.

I did a fork of the library and added code for support of the VHDL Pearl-Diver.

The advantage is that every software working together with dcurl library can make use of the FPGA version of Curl (on Raspberry Pi – for different targets the low level control of SPI has to be replaced).

Link to Github Repository

Compiling and Testing with dcurl

1. Download and install BCM2835 library

# download the latest version of the library, say bcm2835-1.xx.tar.gz, then:
tar zxvf bcm2835-1.xx.tar.gz
cd bcm2835-1.xx
./configure
make
sudo make check
sudo make install

2. Enable „SPI“ under „Interfacing Options“.

sudo raspi-config

3. Load kernel module with modprobe

sudo modprobe spi_bcm2835

4. Check Permissions

pi@raspi:~ $ ls /dev/spidev0.0 -al
crw-rw---- 1 root spi 153, 0 May 3 15:17 /dev/spidev0.0

pi@raspi:~ $ groups
pi adm dialout cdrom sudo audio video plugdev games users input netdev gpio i2c spi

5. Clone and Compile dcurl library

git clone https://github.com/shufps/dcurl
cd dcurl
make BUILD_FPGA=1

6. Test library (for a reason I still don’t know SPI access only with „sudo“ possible).

cd build
sudo ./test-pow_fpga

parallel level detected: 5
Found nonce: 000c9b9c (mask: 00000008)
Time: 321ms  -  MH/s: 12.870

7. If there is no error then everything worked 🙂

 

Support

This project consumed a lot of work and time and financial resources. I would be very happy if some people would consider to leave a small donation:

LLEYMHRKXWSPMGCMZFPKKTHSEMYJTNAZXSAYZGQUEXLXEEWPXUNWBFDWESOJVLHQHXOPQEYXGIRBYTLRWHMJAOSHUY

Discord: pmaxuw#8292

Licence

This project is licensed under the MIT-License